1. Field of the Invention
The present invention relates to semiconductor devices and controlling methods thereof and, in particular, relates to a semiconductor device including an output buffer circuit and a controlling method thereof.
2. Description of Related Art
In semiconductor devices such as DRAM (Dynamic Random Access Memory), an output buffer circuit is provided for outputting a data signal to the outside of the semiconductor device. Some of versatile semiconductor devices, in particular, are configured to be able to select impedance of the output buffer circuit (See Japanese Patent Application Laid-open No. 2006-203405).
As disclosed in Japanese Patent Application Laid-open No. 2006-203405, the output buffer circuit has the structure in which a pull-up buffer circuit consisting of p-channel MOS transistors and a pull-down buffer circuit consisting of n-channel MOS transistors are connected in series. A data terminal is connected to a contact node between the pull-up buffer circuit and the pull-down buffer circuit. When a high-level data signal is outputted from the data terminal, it is controlled in such a manner that the pull-up buffer circuit is turned on and the pull-down buffer circuit is turned off. On the other hand, when a low-level data signal is outputted from the data terminal, it is controlled in such a manner that the pull-up buffer circuit is turned off and the pull-down buffer circuit is turned on.
During a period when the data signal is not outputted from the data terminal, however, it is necessary to allow the output buffer circuit to be in a high impedance state or to function as a termination resistor having predetermined impedance. The function of the output buffer circuit as the termination resistor is referred to as ODT (On Die Termination).
In order to allow the output buffer circuit to be in the high impedance state, it is necessary to turn off both of the pull-up buffer circuit and the pull-down buffer circuit. With DDR3 (Double Data Rate 3) SDRAM (Synchronous DRAM), both of the pull-up buffer circuit and the pull-down buffer circuit need to be turned on when the output buffer circuit performs ODT operation. Thus, it is necessary for the DDR3 SDRAM to deal with four cases in total, that is, the case where only the pull-up buffer circuit is turned on, the case where only the pull-down buffer circuit is turned on, the case where both of the buffer circuits are turned on, and the case where both of the buffer circuit are turned off. Therefore, operation of the pull-up buffer circuit and operation of the pull-down buffer circuit need to be controllable separately.
In the DDR3 SDRAM, a termination level of the data terminal is VDD/2, and therefore it is necessary to allow the output buffer circuit to shift from the high impedance state or the CDT state to an output state of the data signal at timing precisely synchronizing with a clock signal. For this purpose, a control signal allowing the output buffer circuit to be in the high impedance state or the CDT state needs to be inputted in a serializer that generates the data signal in synchronism with the clock signal, which causes the problem that a timing margin of the control signal is small.